Street Fighter Alpha 2 - SDD1 with files folders decompressed

[fandangos]

It is a prototype of the actual game not a prototype of the hack.

It's from before SDD1 being implemented, so it should run like any regular game on the SD2Snes.

[brianvgplayer]

It's also a very early prototype with only a few characters playable.

[leonquest]

It's also a very early prototype with only a few characters playable.

Also, it crashes all the time.

[rocketblast]

Can anyone confirm that there is a working SDD-1 implementation that is coming out?  All I have seen are a few non-game photos of it so far and I'm not sure if it has been implemented into SD2SNES.  Thanks

[sonicjhn]

Can anyone confirm that there is a working SDD-1 implementation that is coming out?  All I have seen are a few non-game photos of it so far and I'm not sure if it has been implemented into SD2SNES.  Thanks

Yes, there's a work in progress for the S-DD1 core for SD2SNES, by a developer called Magno.
Here's his last statement about it from 2 days ago (august 16th):

"magno

Update for S-DD1 development!
I finally could compile firmware on Windows 10, thanks to @James-F and his patience with me. And thanks to all other who offer to help ( @terminator2k2 and @Syboxez )
I couldn't compile snescom/sneslink on Windows 10, though; nevertheless, that's not necessary because no changes are needed for menu.bin
I re-worked sd2snes board to make FPGA's JTAG port accessible from outside; thanks to @ikari_01 for helping me with board layout
I had a tough time making Xilinx Platfom Calbe USB work on windows 10, but finally I could, so now I'm able to debug the FPGA from ISE 14.7 with Chipscope
I also soft-wired my S-DD1 core properly with the rest of the firmware; I commented "snes_addr" module so I now understand which part of address decoding was done there and which part must be kept on the S-DD1 core
Now, I'm optimizing the pipeline because ISE can't get timing closure on the design
That means some signals are delayed too much when routed through the FPGA's logic and wrong values are registered when clock's rising edge arrives to destination register."