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Topics - PityOnU

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FXPAK (SD2SNES) / Implementing GSU Chip (SuperFX) in Verilog
« on: March 12, 2018, 07:28 PM »
I'm working towards my Ph.D. in computer engineering right now, and need to so some sort of VLSI project for one of my graduate courses. I've tasked myself with implementing a working clone of the GSU/SuperFX in Verilog. This could be used in future to allow greater compatibility for sd2snes, and maybe allow for cheap reproduction carts (depending on the size of the resulting logic).

I have my development environment all set up, and am able to compile the sd2snes firmware/menu/FPGA configuration from source. I have started working on implementing the GSU based on the sparse documentation I can find, as well as what is defined within the Higan source code.

However, the chip is more complicated than I was expecting (custom ISA, pipelined, multiple, non-deterministic memory access paths, varying IPC, etc.). If anyone knows any good sources for documentation regarding the chip, I would greatly appreciate them being posted here.

Also, if anyone would like to follow my progress/assist in implementation, let me know. I need to figure out how to work git/Github so I can properly fork the original source and archive changes, and that would give me an extra little push.

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