Author Topic: Implementing GSU Chip (SuperFX) in Verilog  (Read 8465 times)

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Offline PityOnU

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Implementing GSU Chip (SuperFX) in Verilog
« on: March 12, 2018, 07:28 PM »
I'm working towards my Ph.D. in computer engineering right now, and need to so some sort of VLSI project for one of my graduate courses. I've tasked myself with implementing a working clone of the GSU/SuperFX in Verilog. This could be used in future to allow greater compatibility for sd2snes, and maybe allow for cheap reproduction carts (depending on the size of the resulting logic).

I have my development environment all set up, and am able to compile the sd2snes firmware/menu/FPGA configuration from source. I have started working on implementing the GSU based on the sparse documentation I can find, as well as what is defined within the Higan source code.

However, the chip is more complicated than I was expecting (custom ISA, pipelined, multiple, non-deterministic memory access paths, varying IPC, etc.). If anyone knows any good sources for documentation regarding the chip, I would greatly appreciate them being posted here.

Also, if anyone would like to follow my progress/assist in implementation, let me know. I need to figure out how to work git/Github so I can properly fork the original source and archive changes, and that would give me an extra little push.

Offline James-F

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #1 on: March 12, 2018, 08:08 PM »
May I suggest that you have a chat with ikari, he will point you to the right direction.
Ikari may have some half cooked pie so you may not start from scratch.

I hope you're serious, this community deserves more Ph.D's working on stuff.
Who knows,, maybe in the future the credit to SuperFX support on the SD2SNES will go to Prof. PityOnU.  ;)
Mega Everdrive x5, Everdrive 64 v3, Everdrive N8, SD2SNES


Offline iwasaperson

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #3 on: March 12, 2018, 09:49 PM »
Talk to ikari_01 (creator of the SD2SNES), kevtris (creator of many FPGA cores including a SNES core), and jwdonal (creator of VeriSNES and SNES-related documentation).

SNESdev is a fantastic resource for SNES: http://forums.nesdev.com/viewforum.php?f=12&sid=6e23c9d83bf0d6f683ea595999c0bc25

Offline Greg2600

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #4 on: March 13, 2018, 06:06 PM »
Best of luck!

Offline PityOnU

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #5 on: March 13, 2018, 10:13 PM »
May I suggest that you have a chat with ikari, he will point you to the right direction.
Ikari may have some half cooked pie so you may not start from scratch.

I hope you're serious, this community deserves more Ph.D's working on stuff.
Who knows,, maybe in the future the credit to SuperFX support on the SD2SNES will go to Prof. PityOnU.  ;)

Ikari's own website just suggests coming here, and I completely understand that. I'm sure he gets bugged a lot by people looking to contribute, who then end up just dropping off the face of the Earth due to lack of time/skills. I don't want to be one of those annoying people, so I will wait to reach out to him until I have something worth bothering him about. Most of this work can be done completely separately from the sd2snes.

And while I was seriously considering pursuing a faculty position post-graduation, I've "seen behind the curtain" as to how academia actually works, and I really don't think it's for me. At least in my discipline - others are likely much different. That's an entirely different conversation, though.

Dev Book 2:  https://archive.org/stream/SNESDevManual/book2#page/n0/mode/2up

MARIO Patent:  https://docs.google.com/viewer?url=patentimages.storage.googleapis.com/pdfs/US5388841.pdf

Thanks for these! They are exactly what I was hoping to find. Reading through the patent right now - it is incredibly detailed and will help a lot.

Talk to ikari_01 (creator of the SD2SNES), kevtris (creator of many FPGA cores including a SNES core), and jwdonal (creator of VeriSNES and SNES-related documentation).

SNESdev is a fantastic resource for SNES: http://forums.nesdev.com/viewforum.php?f=12&sid=6e23c9d83bf0d6f683ea595999c0bc25

As mentioned above, while I would very much like to talk with those guys some day (I would very much consider them "rock stars" in this area), I will wait until I have something worth bothering about. I will certainly check out that forum, though!

Best of luck!

Thanks! I will try and post here regularly with updates as to what is going on/how it's looking. I would really like to get deep into this, as it is something I am passionate about and certainly have the skills to do.

Unfortunately, the reality is that this is for a course, which at the graduate level is considered a waste of time. Most people just take classes related to their research and regurgitate their paper/WIP from that semester as the "course project" so they don't actually have to do any work. This is expected, and they all get A's.

This is something that is very much outside of my research area, so I'm already doing about 1000% more work than my advisor (boss) deems necessary, so we'll see how far I can get before I get banned from working on it.

Offline protheanbeacon

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #6 on: March 17, 2018, 05:07 AM »
https://board.byuu.org/index.php

Byuu and his forum buddies might be willing to help you Pityonyou.

As I'm sure you may already know byuu is a big deal in the SNES preservation scene because he apparently created the most accurate SNES emulators to date BSNES now retitled Higan.

Then there is Marshall H the creator of the N64 Ultra HDMI board. He was nice enough to communicate with me in email as I had glitches in games to report to him for him to work out a long while back of which he was very grateful to me for as I reported a large amount of games I'd tested on certain firmware of his which likely led to his gratefulness meaning he didn't have to then go test ALL of those games himself.

Plus he even implemented my ingame reset idea for his board.

Now sure he's no SNES expert but the guy is intelligent enough to where he and Kevtris have collaborated together on things and I believe he even gave Kevtris some much needed information about how Kevtris could make scanlines work better on his Analog Super NT project.

https://retroactive.be/forum/viewtopic.php?f=8&t=7&start=470

Anyway here's Marshall's forum.

I know you want to wait until you have something substantial to work with before you bother these "rockstar" type of coders and thats fine but just making you aware of how to get in touch with two more of them.

Lastly, even if you are forced to stop doing this project for school, if you were to continue on with it as a passion project and ended up succeeding you'd of course become a hero to our community here and SNES fans in general plus a veritable "rock star" in your own right making the SD2SNES one step closer to living up to it's full potential in playing damn near every game that was ever made for the system.
« Last Edit: March 17, 2018, 05:12 AM by protheanbeacon »

Offline iwasaperson

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #7 on: March 17, 2018, 05:59 AM »
I think you'll find these "rock star" coders to be extremely friendly and willing to help, regardless of how little you have implemented so far. I know ikari_01 visits this forum on occasion, so he may see this thread, and byuu is very responsive on his forum. Kevtris can probably be contacted pretty easily through AtariAge or perhaps through other means.

I (a much stupider person than you :P) have asked each of these people questions and they have been more than willing to answer.

Offline PityOnU

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #8 on: March 17, 2018, 06:29 AM »
Okay, so I just made an initial commit to my repo with the work I've done so far. It is here if anyone wants to check it out/follow the progress.

I'm trying to follow the original patent as closely as possible, so I've broken everything into blocks named the same as they are in the patent. I've also included citations for locations in the patent which discuss a specific block in the comments wherever possible. Should make it easy for people to jump into an out of if you want to contribute. I've also tried to include in the comments any assumptions I've made which weren't explicitly stated by any source.

There's not much there so far - at least in terms of what needs to be done. Fig. 4A and 4B in the patent can be considered the top level overview for this chip. I've currently only finished block 50, and have made some progress into the blocks related to the cache and cache control.

The "test_stimulus" file includes a bunch of .tcl scripts to use with ISim to verify functionality of the blocks. I've included "test" statements in each of the scripts, which should allow anyone who makes changes to the blocks to verify that they still work as originally intended (if that was the goal, of course). Commenting in these is sketchy at best.

It's been about 5 years since I've done any VLSI work, and I never used Verilog (Americans use VHDL), so I'm still kind of hashing out my coding style. It will probably continue to evolve as I work on this. Some notes on what I've come across:

  • There will needs to be some hacks if we ever want full support for this chip. The FPGA does not support the full 512Kb of RAM used by most games, so only games which use a 256Kb address space will work natively (Yoshi's Island & Star Fox, so not bad). Maybe there is some DRAM hidden elsewhere on the cart? Or maybe the embedded ARM controller can share some of its? I'm not sure.
  • The designers of this chip used a lot of latches to solve timing problems. These aren't really used anymore in modern VLSI, and definitely not in FPGA's. I might have to do some weird things with the clock to get everything working together as it was originally designed.
  • The good news is the chip has dedicated, separate clocks for the main ALU, the multiplier unit, and the memory, with the memory being the main bottleneck originally. Making these available to an FPGA would allow for some very granular overclocking which would work pretty much flawlessly (assuming games we coded as the designers expected).

That's all for now. Just reading through and understanding the patent took the better part of a week, and that was all day every day (spring break). We'll see how/if progress continues from here.

Offline leonquest

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #9 on: March 18, 2018, 07:27 PM »
Hi PityOnYou,

It looks like one of smokemonster's twitter followers coincided with you and also wants to make sfx verilog himself.

What's more,  he would like to work with you! Do you have a twitter?

https://twitter.com/AshEvans81/status/975337316930682880?s=19
Everdrive64 V3 - SD2Snes rev. f - Everdrive N8 fami - MegaEd X3 - PS IO

On my wishlist:
Everdrive GBA - EDGB X3 - Saturn Satisfier

Offline Relikk

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #10 on: March 18, 2018, 09:28 PM »

Offline PityOnU

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #11 on: March 18, 2018, 11:31 PM »
Hi PityOnYou,

It looks like one of smokemonster's twitter followers coincided with you and also wants to make sfx verilog himself.

What's more,  he would like to work with you! Do you have a twitter?

https://twitter.com/AshEvans81/status/975337316930682880?s=19

There are actually a handful of people currently working on this who have reached out to me already. At least a couple already have something up and running on the cart.

However, most of what I have seen so far has emphasized getting things running on the cart over actually designing an accurate replication of the chip. Additionally, reservations over community expectations combined with inexperience in VLSI has stopped others from making their code public domain.

To all of you out there, I highly recommend putting a lot of time and effort into verification of your design. The Xilinx ISE has a built-in simulator - you should use it. Actually putting your design on the cart should be the LAST thing you do, and should be done with the help of ikari himself. If you plan on debugging your design primarily through the cart, then you're going to have a bad time. (Seriously, this chip is WAY too complex).

I also highly encourage you all to make your code public. If you think it is messy/silly/wrong, then that's an even bigger reason to make it public. If other people can see it, then they can provide you feedback so you can fix your mistakes. Better to do it sooner rather than later.

And with those potentially incendiary remarks, I will go back to studying for my midterm.

Offline foldor

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #12 on: March 23, 2018, 10:19 PM »
Have you seen Megari's implementation work? It's all on GitHub here: https://github.com/megari/sd2snes

Offline iwasaperson

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #13 on: March 23, 2018, 10:52 PM »

Online ikari_01

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Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #14 on: March 23, 2018, 10:59 PM »
WTF. That can't be far from a working implementation.