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General => FXPAK (SD2SNES) => Topic started by: PityOnU on March 12, 2018, 07:28 PM

Title: Implementing GSU Chip (SuperFX) in Verilog
Post by: PityOnU on March 12, 2018, 07:28 PM
I'm working towards my Ph.D. in computer engineering right now, and need to so some sort of VLSI project for one of my graduate courses. I've tasked myself with implementing a working clone of the GSU/SuperFX in Verilog. This could be used in future to allow greater compatibility for sd2snes, and maybe allow for cheap reproduction carts (depending on the size of the resulting logic).

I have my development environment all set up, and am able to compile the sd2snes firmware/menu/FPGA configuration from source. I have started working on implementing the GSU based on the sparse documentation I can find, as well as what is defined within the Higan source code.

However, the chip is more complicated than I was expecting (custom ISA, pipelined, multiple, non-deterministic memory access paths, varying IPC, etc.). If anyone knows any good sources for documentation regarding the chip, I would greatly appreciate them being posted here.

Also, if anyone would like to follow my progress/assist in implementation, let me know. I need to figure out how to work git/Github so I can properly fork the original source and archive changes, and that would give me an extra little push.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: James-F on March 12, 2018, 08:08 PM
May I suggest that you have a chat with ikari, he will point you to the right direction.
Ikari may have some half cooked pie so you may not start from scratch.

I hope you're serious, this community deserves more Ph.D's working on stuff.
Who knows,, maybe in the future the credit to SuperFX support on the SD2SNES will go to Prof. PityOnU.  ;)
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: skaman on March 12, 2018, 08:56 PM
Dev Book 2:  https://archive.org/stream/SNESDevManual/book2#page/n0/mode/2up

MARIO Patent:  https://docs.google.com/viewer?url=patentimages.storage.googleapis.com/pdfs/US5388841.pdf
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: iwasaperson on March 12, 2018, 09:49 PM
Talk to ikari_01 (creator of the SD2SNES), kevtris (creator of many FPGA cores including a SNES core), and jwdonal (creator of VeriSNES and SNES-related documentation).

SNESdev is a fantastic resource for SNES: http://forums.nesdev.com/viewforum.php?f=12&sid=6e23c9d83bf0d6f683ea595999c0bc25
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Greg2600 on March 13, 2018, 06:06 PM
Best of luck!
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: PityOnU on March 13, 2018, 10:13 PM
May I suggest that you have a chat with ikari, he will point you to the right direction.
Ikari may have some half cooked pie so you may not start from scratch.

I hope you're serious, this community deserves more Ph.D's working on stuff.
Who knows,, maybe in the future the credit to SuperFX support on the SD2SNES will go to Prof. PityOnU.  ;)

Ikari's own website just suggests coming here, and I completely understand that. I'm sure he gets bugged a lot by people looking to contribute, who then end up just dropping off the face of the Earth due to lack of time/skills. I don't want to be one of those annoying people, so I will wait to reach out to him until I have something worth bothering him about. Most of this work can be done completely separately from the sd2snes.

And while I was seriously considering pursuing a faculty position post-graduation, I've "seen behind the curtain" as to how academia actually works, and I really don't think it's for me. At least in my discipline - others are likely much different. That's an entirely different conversation, though.

Dev Book 2:  https://archive.org/stream/SNESDevManual/book2#page/n0/mode/2up

MARIO Patent:  https://docs.google.com/viewer?url=patentimages.storage.googleapis.com/pdfs/US5388841.pdf

Thanks for these! They are exactly what I was hoping to find. Reading through the patent right now - it is incredibly detailed and will help a lot.

Talk to ikari_01 (creator of the SD2SNES), kevtris (creator of many FPGA cores including a SNES core), and jwdonal (creator of VeriSNES and SNES-related documentation).

SNESdev is a fantastic resource for SNES: http://forums.nesdev.com/viewforum.php?f=12&sid=6e23c9d83bf0d6f683ea595999c0bc25

As mentioned above, while I would very much like to talk with those guys some day (I would very much consider them "rock stars" in this area), I will wait until I have something worth bothering about. I will certainly check out that forum, though!

Best of luck!

Thanks! I will try and post here regularly with updates as to what is going on/how it's looking. I would really like to get deep into this, as it is something I am passionate about and certainly have the skills to do.

Unfortunately, the reality is that this is for a course, which at the graduate level is considered a waste of time. Most people just take classes related to their research and regurgitate their paper/WIP from that semester as the "course project" so they don't actually have to do any work. This is expected, and they all get A's.

This is something that is very much outside of my research area, so I'm already doing about 1000% more work than my advisor (boss) deems necessary, so we'll see how far I can get before I get banned from working on it.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: protheanbeacon on March 17, 2018, 05:07 AM
https://board.byuu.org/index.php

Byuu and his forum buddies might be willing to help you Pityonyou.

As I'm sure you may already know byuu is a big deal in the SNES preservation scene because he apparently created the most accurate SNES emulators to date BSNES now retitled Higan.

Then there is Marshall H the creator of the N64 Ultra HDMI board. He was nice enough to communicate with me in email as I had glitches in games to report to him for him to work out a long while back of which he was very grateful to me for as I reported a large amount of games I'd tested on certain firmware of his which likely led to his gratefulness meaning he didn't have to then go test ALL of those games himself.

Plus he even implemented my ingame reset idea for his board.

Now sure he's no SNES expert but the guy is intelligent enough to where he and Kevtris have collaborated together on things and I believe he even gave Kevtris some much needed information about how Kevtris could make scanlines work better on his Analog Super NT project.

https://retroactive.be/forum/viewtopic.php?f=8&t=7&start=470

Anyway here's Marshall's forum.

I know you want to wait until you have something substantial to work with before you bother these "rockstar" type of coders and thats fine but just making you aware of how to get in touch with two more of them.

Lastly, even if you are forced to stop doing this project for school, if you were to continue on with it as a passion project and ended up succeeding you'd of course become a hero to our community here and SNES fans in general plus a veritable "rock star" in your own right making the SD2SNES one step closer to living up to it's full potential in playing damn near every game that was ever made for the system.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: iwasaperson on March 17, 2018, 05:59 AM
I think you'll find these "rock star" coders to be extremely friendly and willing to help, regardless of how little you have implemented so far. I know ikari_01 visits this forum on occasion, so he may see this thread, and byuu is very responsive on his forum. Kevtris can probably be contacted pretty easily through AtariAge or perhaps through other means.

I (a much stupider person than you :P) have asked each of these people questions and they have been more than willing to answer.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: PityOnU on March 17, 2018, 06:29 AM
Okay, so I just made an initial commit to my repo with the work I've done so far. It is here (https://github.com/PityOnU/SuperFXinVerilog) if anyone wants to check it out/follow the progress.

I'm trying to follow the original patent as closely as possible, so I've broken everything into blocks named the same as they are in the patent. I've also included citations for locations in the patent which discuss a specific block in the comments wherever possible. Should make it easy for people to jump into an out of if you want to contribute. I've also tried to include in the comments any assumptions I've made which weren't explicitly stated by any source.

There's not much there so far - at least in terms of what needs to be done. Fig. 4A and 4B in the patent can be considered the top level overview for this chip. I've currently only finished block 50, and have made some progress into the blocks related to the cache and cache control.

The "test_stimulus" file includes a bunch of .tcl scripts to use with ISim to verify functionality of the blocks. I've included "test" statements in each of the scripts, which should allow anyone who makes changes to the blocks to verify that they still work as originally intended (if that was the goal, of course). Commenting in these is sketchy at best.

It's been about 5 years since I've done any VLSI work, and I never used Verilog (Americans use VHDL), so I'm still kind of hashing out my coding style. It will probably continue to evolve as I work on this. Some notes on what I've come across:


That's all for now. Just reading through and understanding the patent took the better part of a week, and that was all day every day (spring break). We'll see how/if progress continues from here.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: leonquest on March 18, 2018, 07:27 PM
Hi PityOnYou,

It looks like one of smokemonster's twitter followers coincided with you and also wants to make sfx verilog himself.

What's more,  he would like to work with you! Do you have a twitter?

https://twitter.com/AshEvans81/status/975337316930682880?s=19
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Relikk on March 18, 2018, 09:28 PM
(https://media.giphy.com/media/3oKHWikxKFJhjArSXm/giphy.gif)
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: PityOnU on March 18, 2018, 11:31 PM
Hi PityOnYou,

It looks like one of smokemonster's twitter followers coincided with you and also wants to make sfx verilog himself.

What's more,  he would like to work with you! Do you have a twitter?

https://twitter.com/AshEvans81/status/975337316930682880?s=19

There are actually a handful of people currently working on this who have reached out to me already. At least a couple already have something up and running on the cart.

However, most of what I have seen so far has emphasized getting things running on the cart over actually designing an accurate replication of the chip. Additionally, reservations over community expectations combined with inexperience in VLSI has stopped others from making their code public domain.

To all of you out there, I highly recommend putting a lot of time and effort into verification of your design. The Xilinx ISE has a built-in simulator - you should use it. Actually putting your design on the cart should be the LAST thing you do, and should be done with the help of ikari himself. If you plan on debugging your design primarily through the cart, then you're going to have a bad time. (Seriously, this chip is WAY too complex).

I also highly encourage you all to make your code public. If you think it is messy/silly/wrong, then that's an even bigger reason to make it public. If other people can see it, then they can provide you feedback so you can fix your mistakes. Better to do it sooner rather than later.

And with those potentially incendiary remarks, I will go back to studying for my midterm.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: foldor on March 23, 2018, 10:19 PM
Have you seen Megari's implementation work? It's all on GitHub here: https://github.com/megari/sd2snes
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: iwasaperson on March 23, 2018, 10:52 PM
Have you seen Megari's implementation work? It's all on GitHub here: https://github.com/megari/sd2snes
Or Redguy's: https://github.com/RedGuyyyy/sd2snes/tree/gsu
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: ikari_01 on March 23, 2018, 10:59 PM
WTF. That can't be far from a working implementation.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: iwasaperson on March 24, 2018, 02:04 AM
WTF. That can't be far from a working implementation.
Referring to which implementation?

EDIT: As is more than expected since these are incomplete cores, I synthesized both cores and none of the games I tested run. Just to make sure I'm not messing this up, do I just put the fpga_gsu.bit file in the sd2snes folder and that's it, or is there something else I need to do? I'm still expecting zero games to be able to run, but I'd like to know for future testing.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: James-F on March 24, 2018, 08:38 AM
Looks like RedGuyyyy is very active in his GSU implementation, but he keeps it "under the table" for a good reason.
I wish him the best of luck making it work.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: leonquest on March 24, 2018, 02:28 PM
WTF. That can't be far from a working implementation.

Can you use any of the 2 in SD2Snes?
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: ikari_01 on March 24, 2018, 11:58 PM
Referring to which implementation?
RedGuy's specifically. It looks quite elaborate.

do I just put the fpga_gsu.bit file in the sd2snes folder and that's it, or is there something else I need to do?
You also need a firmware that is aware of SuperFX games and will actually attempt to load fpga_gsu.bit into the FPGA. ;) I'm guessing RedGuy's fork would have something like that prepared.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: leonquest on March 25, 2018, 12:30 AM
Referring to which implementation?
RedGuy's specifically. It looks quite elaborate.

do I just put the fpga_gsu.bit file in the sd2snes folder and that's it, or is there something else I need to do?
You also need a firmware that is aware of SuperFX games and will actually attempt to load fpga_gsu.bit into the FPGA. ;) I'm guessing RedGuy's fork would have something like that prepared.

I want to test the hell out of that,  how would I go about it?
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: redguy on March 25, 2018, 12:54 AM
The firmware changes aren't checked in, yet.  It goes off in the weeds almost immediately on star fox so there's not much to see.  It does run some basic self-checking assembly microbenchmarks including ones that test PLOT and RPIX bitmap instructions.

I will start another thread on the topic if it gets to the point where it can run something.  At this point it's hard to tell if it will all fit in the FPGA as currently implemented so I don't want to set expectations too high.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: leonquest on March 25, 2018, 01:24 AM
The firmware changes aren't checked in, yet.  It goes off in the weeds almost immediately on star fox so there's not much to see.  It does run some basic self-checking assembly microbenchmarks including ones that test PLOT and RPIX bitmap instructions.

I will start another thread on the topic if it gets to the point where it can run something.  At this point it's hard to tell if it will all fit in the FPGA as currently implemented so I don't want to set expectations too high.

That's really cool sir,  thank you for doing this.

I find it curious that there are 4 guys trying to implement gsu-1 on the SD2Snes and not a single one interested in SA-1, why is there no love for SA-1?
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: animeloverxX93 on March 25, 2018, 01:25 AM
Hey, just registered because I was lurking around for quite some time now.

That's great news!
However, since SA1 is still a thing, doesn't that mean that the SD2SNES will inevitably need to get an FPGA revision at a point?
I'm by no means a programmer, so I have little to no knowledge regarding things like this, but what can be done to (or rather, is necessary) for that to happen, and how feasible would be such an undertaking?

I will refrain from further questions, since I don't want to derail this thread anymore.
Whatever the case, I will be looking forward further support for the SD2SNES and its future implementations. :)


Edit: Oh well, got ninja'd pertaining the SA1.  ;D
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: FeverDrive on March 25, 2018, 06:44 AM
Great  8)
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: jonnnlad on March 25, 2018, 09:01 AM
Holy shit - subscribed!

Gods speed devs!
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: iwasaperson on March 25, 2018, 07:47 PM
Just modified the firmware to accept the GSU FPGA configuration (good thing I know C :P). Still just a black screen on everything (with both cores). I was hoping to see a glitchy mess in Star Fox :(

I know it's reading the FPGA core since GSU games take a bit longer to load (like when loading Cx4 games).

EDIT: Dirt Racer boots, but crashes instantly. DOOM gets to the menu, but crashes when it tries to render anything. Basically whenever the GSU is trying to be used, it crashes (go figure :P)
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: ka55 on March 25, 2018, 10:36 PM
Just modified the firmware to accept the GSU FPGA configuration (good thing I know C :P). Still just a black screen on everything (with both cores). I was hoping to see a glitchy mess in Star Fox :(

I know it's reading the FPGA core since GSU games take a bit longer to load (like when loading Cx4 games).

EDIT: Dirt Racer boots, but crashes instantly. DOOM gets to the menu, but crashes when it tries to render anything. Basically whenever the GSU is trying to be used, it crashes (go figure :P)

please send this firmware for me to test on my sd2snes.
thanks.

por favor, envie este firmware para eu testar no meu sd2snes.
thanks.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: FeverDrive on March 25, 2018, 11:22 PM
I want to test the hell out of that,  how would I go about it?
please send this firmware for me to test on my sd2snes.
thanks.
There's no use for us users to test this incomplete and non-functioning implementation... let's wait for the developers to actually make something usable first.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: ka55 on March 25, 2018, 11:29 PM
I want to test the hell out of that,  how would I go about it?
please send this firmware for me to test on my sd2snes.
thanks.
There's no use for us users to test this incomplete and non-functioning implementation... let's wait for the developers to actually make something usable first.
OK.
Thanks. ;D
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: PityOnU on March 26, 2018, 08:20 AM
Just a quick update - put a good 3-4 hours into mine today. Cleaned up the organization a bit, renamed files, added comments, etc.

Main ALU and instruction cache can be considered complete and tested (at least for now). Started work on the register bank.

I'm very glad there are others working on this - hopefully it will inspire me to work harder in the spirit of competition!
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: jonnnlad on March 26, 2018, 11:23 AM
We're also very glad :)

Even just reading the updates is great, even if no "progress" to the average joe (moi) is obvious

Appreciated!

Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: marcus.miranda on March 26, 2018, 04:51 PM
I'm a long time lurker around here and I just signed up to be able to subscribe in this topic.
I wish the best of luck to all who's committed in creating an implementation of GSU in SD2SNES.

Cheers!
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Greg2600 on March 26, 2018, 05:08 PM
Amazing that we went from nobody touching this to now a handful.  Obviously it might be better to have a cooperative effort, but as someone who writes some code, when I see my co-worker's, I'm often like what the hell are you doing here???
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: megari on March 26, 2018, 06:52 PM
My implementation is very, very incomplete and not integrated properly. It also has such serious design issues that I am going to basically restart from scratch on a less specific platform (probably a DE-10 Nano board). I am happy to learn that there are others working towards an FPGA implementation of the GSU. I have such a lot to learn to someday be able to get my implementation to actually do something useful.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: leonquest on March 26, 2018, 09:00 PM
Amazing that we went from nobody touching this to now a handful.  Obviously it might be better to have a cooperative effort, but as someone who writes some code, when I see my co-worker's, I'm often like what the hell are you doing here???

True, but they should probably do well in asking byuu for help, since he's already familiar with emulation of the chip, so it wouldn't hurt to ask him for directions or tips.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Arnold101 on March 27, 2018, 03:26 AM
Just a quick update - put a good 3-4 hours into mine today. Cleaned up the organization a bit, renamed files, added comments, etc.

Main ALU and instruction cache can be considered complete and tested (at least for now). Started work on the register bank.

I'm very glad there are others working on this - hopefully it will inspire me to work harder in the spirit of competition!
8) best wishes, great!
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: PityOnU on March 27, 2018, 06:33 AM
Just another update - spent a long time working on this today. Wrapped up the register block (implementation, verification, etc.). It is up on the Github now. Didn't yet get a chance to add comments with documentation - will do it in the morning.

True, but they should probably do well in asking byuu for help, since he's already familiar with emulation of the chip, so it wouldn't hurt to ask him for directions or tips.

Eh. Good code documents itself, and in such a sense byuu has already made a ton of documentation available to the community. Between that and the patent, I'm not really sure as to what would be gained by pestering the guy.

Amazing that we went from nobody touching this to now a handful.  Obviously it might be better to have a cooperative effort, but as someone who writes some code, when I see my co-worker's, I'm often like what the hell are you doing here???

For team-based development, the work needs to be modularized and divided up between members as blocks with defined interfaces. Then everybody can work individually on their block, their way, and then recombine everything at the end. If you don't do that, you end up with different members accidentally zapping each others code sections, as they don't fully understand the madness behind then.

The biggest problem right now is that most people have begun and continued their work on this as huge, monolithic Verilog files that stretch on for hundreds or thousands of lines. Something like that would be very difficult for me to help debug, to say nothing of actually contributing useful work.

Because of the above, I've tried to keep my code blocks (https://github.com/PityOnU/SuperFXinVerilog) small, verified, and compliant to the naming conventions and interfaces outlined in the patent. If anyone would like to help contributing, feel free to just pick a figure/block that isn't done yet and go! Should be pretty easy to add your block in when you are done. Verilog is pretty easy to pick up, and the patent is US patent #5,388,841 and can be found on Google Scholar. The Xilinx ISE is available (for free) here (https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html).
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: jonnnlad on March 27, 2018, 11:09 AM
I'm happy (i'm sure lots of others are too) to donate to the cause to help buy SD2SNES/consoles/coffee/whatever
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: marcus.miranda on March 27, 2018, 03:09 PM
I'm happy (i'm sure lots of others are too) to donate to the cause to help buy SD2SNES/consoles/coffee/whatever
I share the same feeling here!
I'm a software engineer but since I don't have any "proficiency" in VHDL this is the best way I can help, aside from "volunteering" as a guinea pig, if needed! :)

Cheers!
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: PityOnU on March 28, 2018, 06:18 AM
Quick update for today - spent a lot of time on the plotter block. A bit of an enigma there, but I'm starting to decode it. Got the color matrix circuit (figure 7 block 206) mostly up and running, but just now realized that the SuperFX stores the framebuffer in a different format than the SNES proper. Ugh. Seems like some rewrites are in the near future...

Headed home to drown my sorrows in a nice tall glass of Mtn DewTM.

I'm happy (i'm sure lots of others are too) to donate to the cause to help buy SD2SNES/consoles/coffee/whatever

I appreciate the offer, but I have pretty much everything I need for this right now.

The biggest limitation I actually have right now is time. I won't be able to work on this again until at least this weekend, and even then I have paper deadlines coming up, which are far more critical in the grand scheme of things.

The most useful thing for me right now would be others pitching in on the project. Assuming the details of the patent are followed, any newcomers wouldn't even need to look at anything I've written so far - they could just jump in on whatever section hadn't been implemented yet. Wiring them up together afterwards is actually super easy (if tedious). If anyone out there is interested, you can be certain that you receive any credit that is due for any contributions you make.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: eatnumber1 on April 02, 2018, 10:46 AM
For possibly getting more memory for the SuperFX chip, have you thought about sharing the memory between the various cartridge-only chips that the SD2SNES implements? As far as I know, no games ever made use more than one special chip at a time (well, plus the MSU-1), so if you e.g. share memory between the CX4 and SuperFX you'd likely be able to get more memory.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: FeverDrive on April 02, 2018, 10:36 PM
For possibly getting more memory for the SuperFX chip, have you thought about sharing the memory between the various cartridge-only chips that the SD2SNES implements? As far as I know, no games ever made use more than one special chip at a time (well, plus the MSU-1), so if you e.g. share memory between the CX4 and SuperFX you'd likely be able to get more memory.
Do you know how an FPGA works?
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: eatnumber1 on April 03, 2018, 12:37 AM
Hi FeverDrive, when responding to me, please respond to my points directly rather than via an Ad Hominem [1] attack.

Responding directly, I believe that the CX4's RAM is defined at verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v [2] using a common library provided by Xilinx. As long as the two chips have compatible memory (e.g. same bus widths, etc.), and the two chips don't attempt to drive them at the same time, you should be able to hook them up together.

[1]: https://en.wikipedia.org/wiki/Ad_hominem (https://en.wikipedia.org/wiki/Ad_hominem)
[2]: https://github.com/mrehkopf/sd2snes/blob/develop/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v (https://github.com/mrehkopf/sd2snes/blob/develop/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v)
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Tevlar on April 03, 2018, 12:59 AM
Btw

Kevtris and Smokemonster hangs out on https://discord.gg/EX57xnF pretty much daily
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: eatnumber1 on April 03, 2018, 01:07 AM
Thanks for the tip Tevlar. As far as I know however, neither are working on special chip implementations (or am I mistaken?)
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Arnold101 on April 04, 2018, 05:16 PM
other updates?
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Eyedunno on April 04, 2018, 09:40 PM
other updates?
Nope *whistles*

This other thread is up to 11 pages now for some reason though. Super weird.
http://krikzz.com/forum/index.php?topic=7451.150 (http://krikzz.com/forum/index.php?topic=7451.150)
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: ikari_01 on April 05, 2018, 12:00 AM
Hi!

For possibly getting more memory for the SuperFX chip, have you thought about sharing the memory between the various cartridge-only chips that the SD2SNES implements?

It's not necessary: The firmware consists of several FPGA bitfiles - depending on the requested game it will reconfigure the FPGA with the corresponding bitfile. There are dedicated bitfiles for DSPx+BS-X+S-RTC, Cx4, OBC1, and now GSU thanks to RedGuy. So each of these cores already has the entire FPGA's resources available to itself.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: infidelity on April 05, 2018, 12:42 AM
Wow, incredible!
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: eatnumber1 on April 05, 2018, 01:08 AM
It's not necessary: The firmware consists of several FPGA bitfiles - depending on the requested game it will reconfigure the FPGA with the corresponding bitfile. There are dedicated bitfiles for DSPx+BS-X+S-RTC, Cx4, OBC1, and now GSU thanks to RedGuy. So each of these cores already has the entire FPGA's resources available to itself.

Aha, I see. Clever! Thanks for the info.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: FartPuff on April 06, 2018, 03:21 PM
Correct me if I'm wrong.  The gate capacity problem is considered when you want to run several chips and features simultaneously, like SuperFX and MSU-1

Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: iwasaperson on April 06, 2018, 06:14 PM
Correct me if I'm wrong.  The gate capacity problem is considered when you want to run several chips and features simultaneously, like SuperFX and MSU-1

Correct, although Redguy's SuperFX core already supports MSU-1.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Arnold101 on April 07, 2018, 03:35 AM
Correct me if I'm wrong.  The gate capacity problem is considered when you want to run several chips and features simultaneously, like SuperFX and MSU-1

Correct, although Redguy's SuperFX core already supports MSU-1.
redguy is a genious
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: PityOnU on April 07, 2018, 08:31 PM
other updates?

Nope *whistles*

This other thread is up to 11 pages now for some reason though. Super weird.
http://krikzz.com/forum/index.php?topic=7451.150 (http://krikzz.com/forum/index.php?topic=7451.150)

This thread was targeting a gate-level clone of the SuperFX chip. Development has been ceased because redguy's RTL clone is near-complete, making this effort redundant. His is also fully integrated into the sd2snes firmware already, whereas this one was still entirely independent, requiring a great deal more effort down the line to get up and running on the cart.

Some may argue that a gate-level clone is important to have for full accuracy, but the fact of the matter is that it ends up being an order of magnitude (or more) additional work for the same functionality at the end of the day. Redguy's implementation is essentially a Verilog translation of the C code in higan, which is already considered to be near 100% accuracy for the <12 games that actually used the chip, so that is definitely the way to go in this case.

Mods, feel free to close or lock this thread.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Theta55 on April 08, 2018, 12:55 AM
Got the sd2snes with this on the super nt. Everything working just yoshi's island Kamek's Revenge crashes and one of the star fox 2 patched games. I just patched the yoshi's island hacks and im ready to put on the cart.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: SmokeMonster on April 08, 2018, 01:22 AM
v2.0 Kamek's Revenge works and all Star Fox/SF2 hacks work.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Arnold101 on April 08, 2018, 03:23 AM
other updates?

Nope *whistles*

This other thread is up to 11 pages now for some reason though. Super weird.
http://krikzz.com/forum/index.php?topic=7451.150 (http://krikzz.com/forum/index.php?topic=7451.150)

This thread was targeting a gate-level clone of the SuperFX chip. Development has been ceased because redguy's RTL clone is near-complete, making this effort redundant. His is also fully integrated into the sd2snes firmware already, whereas this one was still entirely independent, requiring a great deal more effort down the line to get up and running on the cart.

Some may argue that a gate-level clone is important to have for full accuracy, but the fact of the matter is that it ends up being an order of magnitude (or more) additional work for the same functionality at the end of the day. Redguy's implementation is essentially a Verilog translation of the C code in higan, which is already considered to be near 100% accuracy for the <12 games that actually used the chip, so that is definitely the way to go in this case.

Mods, feel free to close or lock this thread.
sorry for that. You can work on the sa1 chip still
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: Theta55 on April 09, 2018, 12:00 AM
v2.0 Kamek's Revenge works and all Star Fox/SF2 hacks work.
Thanks i googled 2.0 and found it on smwcentral.net. romhacking.net has the older version.
Title: Re: Implementing GSU Chip (SuperFX) in Verilog
Post by: AlxUnderBase on April 09, 2018, 06:43 PM

Mods, feel free to close or lock this thread.
[/quote]

Looking forward buddy !