Author Topic: Implementing GSU Chip (SuperFX) in Verilog  (Read 15902 times)

0 Members and 1 Guest are viewing this topic.

Offline jonnnlad

  • Newbie
  • *
  • Posts: 8
  • Karma: +1/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #30 on: March 26, 2018, 11:23 AM »
We're also very glad :)

Even just reading the updates is great, even if no "progress" to the average joe (moi) is obvious

Appreciated!


Offline marcus.miranda

  • Newbie
  • *
  • Posts: 9
  • Karma: +0/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #31 on: March 26, 2018, 04:51 PM »
I'm a long time lurker around here and I just signed up to be able to subscribe in this topic.
I wish the best of luck to all who's committed in creating an implementation of GSU in SD2SNES.

Cheers!

Offline Greg2600

  • Sr. Member
  • ****
  • Posts: 267
  • Karma: +5/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #32 on: March 26, 2018, 05:08 PM »
Amazing that we went from nobody touching this to now a handful.  Obviously it might be better to have a cooperative effort, but as someone who writes some code, when I see my co-worker's, I'm often like what the hell are you doing here???

Offline megari

  • Newbie
  • *
  • Posts: 10
  • Karma: +4/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #33 on: March 26, 2018, 06:52 PM »
My implementation is very, very incomplete and not integrated properly. It also has such serious design issues that I am going to basically restart from scratch on a less specific platform (probably a DE-10 Nano board). I am happy to learn that there are others working towards an FPGA implementation of the GSU. I have such a lot to learn to someday be able to get my implementation to actually do something useful.

Offline leonquest

  • Sr. Member
  • ****
  • Posts: 390
  • Karma: +19/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #34 on: March 26, 2018, 09:00 PM »
Amazing that we went from nobody touching this to now a handful.  Obviously it might be better to have a cooperative effort, but as someone who writes some code, when I see my co-worker's, I'm often like what the hell are you doing here???

True, but they should probably do well in asking byuu for help, since he's already familiar with emulation of the chip, so it wouldn't hurt to ask him for directions or tips.
Everdrive64 V3 - SD2Snes rev. f - Everdrive N8 fami - MegaEd X3 - PS IO

On my wishlist:
Everdrive GBA - EDGB X3 - Saturn Satisfier

Offline Arnold101

  • Sr. Member
  • ****
  • Posts: 353
  • Karma: +4/-1
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #35 on: March 27, 2018, 03:26 AM »
Just a quick update - put a good 3-4 hours into mine today. Cleaned up the organization a bit, renamed files, added comments, etc.

Main ALU and instruction cache can be considered complete and tested (at least for now). Started work on the register bank.

I'm very glad there are others working on this - hopefully it will inspire me to work harder in the spirit of competition!
8) best wishes, great!

Offline PityOnU

  • Newbie
  • *
  • Posts: 9
  • Karma: +5/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #36 on: March 27, 2018, 06:33 AM »
Just another update - spent a long time working on this today. Wrapped up the register block (implementation, verification, etc.). It is up on the Github now. Didn't yet get a chance to add comments with documentation - will do it in the morning.

True, but they should probably do well in asking byuu for help, since he's already familiar with emulation of the chip, so it wouldn't hurt to ask him for directions or tips.

Eh. Good code documents itself, and in such a sense byuu has already made a ton of documentation available to the community. Between that and the patent, I'm not really sure as to what would be gained by pestering the guy.

Amazing that we went from nobody touching this to now a handful.  Obviously it might be better to have a cooperative effort, but as someone who writes some code, when I see my co-worker's, I'm often like what the hell are you doing here???

For team-based development, the work needs to be modularized and divided up between members as blocks with defined interfaces. Then everybody can work individually on their block, their way, and then recombine everything at the end. If you don't do that, you end up with different members accidentally zapping each others code sections, as they don't fully understand the madness behind then.

The biggest problem right now is that most people have begun and continued their work on this as huge, monolithic Verilog files that stretch on for hundreds or thousands of lines. Something like that would be very difficult for me to help debug, to say nothing of actually contributing useful work.

Because of the above, I've tried to keep my code blocks small, verified, and compliant to the naming conventions and interfaces outlined in the patent. If anyone would like to help contributing, feel free to just pick a figure/block that isn't done yet and go! Should be pretty easy to add your block in when you are done. Verilog is pretty easy to pick up, and the patent is US patent #5,388,841 and can be found on Google Scholar. The Xilinx ISE is available (for free) here.

Offline jonnnlad

  • Newbie
  • *
  • Posts: 8
  • Karma: +1/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #37 on: March 27, 2018, 11:09 AM »
I'm happy (i'm sure lots of others are too) to donate to the cause to help buy SD2SNES/consoles/coffee/whatever

Offline marcus.miranda

  • Newbie
  • *
  • Posts: 9
  • Karma: +0/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #38 on: March 27, 2018, 03:09 PM »
I'm happy (i'm sure lots of others are too) to donate to the cause to help buy SD2SNES/consoles/coffee/whatever
I share the same feeling here!
I'm a software engineer but since I don't have any "proficiency" in VHDL this is the best way I can help, aside from "volunteering" as a guinea pig, if needed! :)

Cheers!

Offline PityOnU

  • Newbie
  • *
  • Posts: 9
  • Karma: +5/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #39 on: March 28, 2018, 06:18 AM »
Quick update for today - spent a lot of time on the plotter block. A bit of an enigma there, but I'm starting to decode it. Got the color matrix circuit (figure 7 block 206) mostly up and running, but just now realized that the SuperFX stores the framebuffer in a different format than the SNES proper. Ugh. Seems like some rewrites are in the near future...

Headed home to drown my sorrows in a nice tall glass of Mtn DewTM.

I'm happy (i'm sure lots of others are too) to donate to the cause to help buy SD2SNES/consoles/coffee/whatever

I appreciate the offer, but I have pretty much everything I need for this right now.

The biggest limitation I actually have right now is time. I won't be able to work on this again until at least this weekend, and even then I have paper deadlines coming up, which are far more critical in the grand scheme of things.

The most useful thing for me right now would be others pitching in on the project. Assuming the details of the patent are followed, any newcomers wouldn't even need to look at anything I've written so far - they could just jump in on whatever section hadn't been implemented yet. Wiring them up together afterwards is actually super easy (if tedious). If anyone out there is interested, you can be certain that you receive any credit that is due for any contributions you make.

Offline eatnumber1

  • Newbie
  • *
  • Posts: 4
  • Karma: +0/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #40 on: April 02, 2018, 10:46 AM »
For possibly getting more memory for the SuperFX chip, have you thought about sharing the memory between the various cartridge-only chips that the SD2SNES implements? As far as I know, no games ever made use more than one special chip at a time (well, plus the MSU-1), so if you e.g. share memory between the CX4 and SuperFX you'd likely be able to get more memory.

Offline FeverDrive

  • Hero Member
  • *****
  • Posts: 1141
  • Karma: +46/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #41 on: April 02, 2018, 10:36 PM »
For possibly getting more memory for the SuperFX chip, have you thought about sharing the memory between the various cartridge-only chips that the SD2SNES implements? As far as I know, no games ever made use more than one special chip at a time (well, plus the MSU-1), so if you e.g. share memory between the CX4 and SuperFX you'd likely be able to get more memory.
Do you know how an FPGA works?
And so I go fast.

Offline eatnumber1

  • Newbie
  • *
  • Posts: 4
  • Karma: +0/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #42 on: April 03, 2018, 12:37 AM »
Hi FeverDrive, when responding to me, please respond to my points directly rather than via an Ad Hominem [1] attack.

Responding directly, I believe that the CX4's RAM is defined at verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v [2] using a common library provided by Xilinx. As long as the two chips have compatible memory (e.g. same bus widths, etc.), and the two chips don't attempt to drive them at the same time, you should be able to hook them up together.

[1]: https://en.wikipedia.org/wiki/Ad_hominem
[2]: https://github.com/mrehkopf/sd2snes/blob/develop/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v

Offline Tevlar

  • Newbie
  • *
  • Posts: 1
  • Karma: +0/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #43 on: April 03, 2018, 12:59 AM »
Btw

Kevtris and Smokemonster hangs out on https://discord.gg/EX57xnF pretty much daily

Offline eatnumber1

  • Newbie
  • *
  • Posts: 4
  • Karma: +0/-0
    • View Profile
Re: Implementing GSU Chip (SuperFX) in Verilog
« Reply #44 on: April 03, 2018, 01:07 AM »
Thanks for the tip Tevlar. As far as I know however, neither are working on special chip implementations (or am I mistaken?)
« Last Edit: April 03, 2018, 01:10 AM by eatnumber1 »