It's not. Not enough block RAM.
Regardless of whether the FPGA is big enough or not, a minimal, inaccurate implementation of the SA-1 would still be possible so that it could run all released games and maybe those SMW ROM hacks as well. Implementing the entire 65816 would be a large task, and I'm not sure if that would fit in the FPGA. Maybe if jwdonal or kevtris would like to share their implementations then we could see a more accurate version be developed (as far as I understand, the SA-1 is an overglorified 65816 + CIC).
Indeed, and I still have it planned as a fallback. Could always happen that the power goes out or the SNES is switched off too soon while saving. Also for games that permanently keep changing the SRAM content it would be probably better to rely on than doing periodic saving.
How long does the SD2SNES normally take to save games? I've never had a problem with saving and semi-quickly powering off. A fallback like that would be a nice feature though.
And completely unrelated, how hard would it be to implement the SPC7110? The SD2SNES already has an RTC, and from what I can tell, it is a compression chip. I'd really like to play the recently released Far East of Eden Zero. Would it be possible to decompress the game (ie Star Ocean) and have it access the build in RTC instead of implementing the chip?