Perhaps another way to think of it is like RAM. (It's not, I know.) You've got different modules that all take differing amounts of RAM to load into memory, so you have to pick and choose which ones to load in. Given that SA1 would take up all the "RAM", there's no room left to load in the MSU module.
Now, substitute "RAM" with "logic blocks", and I think that gives the picture.
Also, a personal request: there's no sense in being rude to folks that don't understand how all this works. It might get old explaining things, but even then, we can be nice in pointing folks to the answer if it's a question that has already been asked.
On top of that, once again, I'd like to thank both ikari and Redguy (and any other folks that may have contributed!) for all their hard work. I'm still flabbergasted that this might be possible after all.